1. Field of the Invention
The present invention relates to a liquid crystal display apparatus which incorporates a "chips on glass" (COG) system in which integrated circuit (IC) chips are directly mounted onto a glass substrate. More particularly, the present invention relates to a glass connector for applying signals to the IC chips and a method of making such a liquid crystal display apparatus.
2. Description of Related Art
Since a liquid crystal display apparatus has advantages including being light weight, having a low small thickness, low power consumption and so on, its applications have steadily increased. A liquid crystal display apparatus includes a picture display having picture elements or pixels of liquid crystal arranged in a matrix pattern, and driving IC chips, (hereinafter referred to as D-IC chips), for driving the liquid crystal display. Recently, a liquid crystal display apparatus has been manufactured using the COG system in which D-IC chips are directly mounted on the edge of a glass substrate. Also, the COG type liquid crystal panel makes use of a flexible printed circuit (FPC) film for applying signals to the D-IC chips. The FPC film is adhered onto the glass substrate using a conductive resin. The FPC film includes a single conductive layer or multiple conductive layers made from a metal material interposed between a soft or flexible material layer such as polyimide.
However, the FPC film having multiple conductive layers increases the manufacturing cost of the liquid crystal display apparatus and causes an unstable and unreliable electrical connection with the glass substrate. On the other hand, the single conductive layer of the FPC film is used with separate wiring provided on the glass substrate, so that it is capable of reducing the manufacturing cost of the liquid crystal display apparatus. However it may cause problems of poor connection, signal delay and so on. The problems in the COG type liquid crystal display apparatus using such FPC films will be more apparent from the following description with reference to FIG. 1 to FIG. 4.
FIG. 1 schematically illustrates a conventional COG type liquid crystal display apparatus using FPC films 8A and 8B each having two conductive layers. FIG. 2 is a sectional view of the liquid crystal display apparatus taken along line A-A' in FIG. 1. As shown in FIG. 1, the COG type liquid crystal display apparatus includes an upper glass substrate 4 provided on top of a lower glass substrate 2, gate driving IC chips 6 mounted on the right edge of the lower glass substrate 2, and data driving IC chips 10 mounted on the lower edge of the lower glass substrate 2. Each pixel consisting of liquid crystal cells and thin film transistors TFTs is formed between the lower glass substrate 2 and the upper glass substrate 4 in a matrix pattern. The gate D-IC chips 6 apply gate control signals to gate electrodes included in the pixel matrix, thereby driving the TFTS. The data D-IC chips 10 apply data signals to the source electrodes included in the pixel matrix, thereby controlling the light transmissivity of liquid crystal cells. The pixel matrix displays a picture corresponding to video signals supplied via the gate D-IC chips 6 and the data D-IC chips 10.
Further, gate FPC film 8A is provided at the right edge of the lower glass substrate 2 and is located adjacent to the gate D-IC chips 6. Data FPC film 8B is provided at the lower edge of the lower glass substrate 2 and located adjacent to the data D-IC chips 10. The gate FPC film 8A transfers electrical signals including timing control signals, voltage signals and so on from the control circuitry (not shown) to the gate D-IC chips 6. The data FPC film 8B transfers electrical signals including timing control signals, video signals, voltage signals and so on from the control circuitry to the data D-IC chips 10. In order to transfer so many signals, the gate FPC film 8A and the data FPC film 8B each usually has two conductive layers, but can have more than four conductive layers when the number of electrical signals is above 40.
FIG. 2 illustrates a section of the COG type liquid crystal display apparatus taken along line II--II in FIG. 1. As shown in FIG. 2, the D-IC chip 6 is mounted between the upper glass substrate 4 and the FPC film 8A. Also, the D-IC chip 6 is electrically connected to an input wiring electrode 14 and the output wiring electrode 16 via an anisotropic conductive film 18. The FPC film 8A consists of a first conductive layer 20 and a second conductive layer 22 provided at the lower surface and the upper surface of a base film 26, respectively. A protective film 24 is wound around the base film 26 and the first and second conductive layers 20 and 22. At this time, one end of the first conductive layer 20 and one end of the second conductive layer 22 are left exposed by the protective film 24. The exposed end of the first conductive layer 20 is electrically connected to an input pad via the anisotropic conductive film 18. The second conductive layer 22 is electrically connected to the first conductive layer 20 via a contact 28 passing through the base film 26.
A multiple layer structure of the FPC film installed at the edge of the lower glass substrate increases the manufacturing cost as a portion adhered to the lower glass substrate is lengthened and as the number of conductive layers increases. Also, it is difficult to arrange the FPC film on the lower glass substrate because of its high degree of softness or flexibility. In addition, the FPC film causes a poor connection produced by a thermal impact because the base film has a much greater thermal expansion coefficient than the glass substrate. Such a poor connection frequently occurs due to a large tolerance occurring when conductive layers having a thickness above 18 mm are patterned.
Accordingly, a COG type liquid crystal display apparatus has been suggested as shown in FIG. 3 that uses a single layer of FPC film instead of the multiple layer structure of the FPC film causing the above problems.
Referring now to FIG. 3, another COG type liquid crystal display apparatus includes a first signal wiring 30 provided at the right edge of a lower glass substrate 2, second signal wiring 32 provided at the lower edge of the lower glass substrate 2, and a FPC film 8 provided at the lower right corner of the lower glass substrate 2 so as to be electrically connected to first and second signal wirings 30 and 32. First signal wiring 30 is connected to gate D-IC chips 6 disposed between an upper glass substrate 4 and the first signal wiring 30 to transfer electrical signals from the FPC film 8 to the gate D-IC chips 6. Likewise, second signal wiring 32 is connected to the data D-IC chips 10 disposed between the upper glass substrate 4 and the second wiring 32 to transfer electrical signals from the FPC film 8 to the data D-IC chips 10.
The FPC film 8 is electrically connected to control circuitry (not shown) via a mechanical device, e.g., a connector. Also, the FPC film 8 includes only one conductive layer because it is not connected to the gate D-IC chips 6 and the data D-IC chips 10. As a result, the COG type liquid crystal display apparatus is capable of reducing the manufacturing cost of the FPC film and therefore, the overall manufacturing cost of the COG type liquid crystal display apparatus, while also significantly reducing poor electrical connections.
FIG. 4 illustrates a section of the COG type liquid crystal display apparatus taken along line IV--IV in FIG. 3. The D-IC chip 6 is electrically connected to an input wiring electrode 14 and an output wiring electrode 16 via an anisotropic conductive film 18. The signal wiring 30 is positioned at the upper portion of the input wiring electrode 14. An insulating layer 34 is disposed between the signal wiring 30 and the input wiring electrode 14. A protective film 36 is coated on the signal wiring 30 and the upper portion of the exposed insulating layer 34. Further, the signal wiring 30 is electrically connected to the input wiring electrode 14 via a contact which passes through the insulating layer 34.
As described above, the signal wiring positioned at the upper portion of the input wiring electrode 14 is made from a high resistance material having a resistance equal to the resistance of the material used to form the gate, the source and the drain of the TFT. Further, the insulating layer 34 for electrically separating the input wiring electrode 14 from the signal wiring 30 is provided with a capacitor located between the input wiring 30 electrode 14 and the signal wiring. As a result, it is impossible to avoid delay in delivery of electrical signals to be delivered via the signal wiring to the D-IC chips. Also, poor connections between the input wiring electrode 30 and the signal wiring 14 occur as a result of a poor quality of contact and a poor deposition of the insulating film.